Oftentimes, during integrated circuit (IC) manufacturing, different regions of the same layer are patterned differently and, particularly, patterned with shapes having different widths and/or different pitches. For example, different regions of a polycrystalline semiconductor layer (e.g., a polysilicon or other suitable polycrystalline semiconductor layer) may be patterned with relatively thick gate structures having a first pitch for long channel field effect transistors (FETs), with relatively thin gate structures having a second pitch for short channel FETs, etc. Similarly, different regions of a monocrystalline semiconductor layer (e.g., a silicon layer or other suitable monocrystalline semiconductor layer) may be patterned with relatively thick semiconductor fins having a first pitch for tri-gate FETs, with relatively thin semiconductor fins having a second pitch for dual-gate FETs (also referred to herein as fin-type FETs or finFETs), with planar semiconductor bodies for planar FETs, etc. It should be understood that these examples are not intended to be limiting and, during IC manufacturing, different regions of other material layers (e.g., dielectric layers, metal layers, etc.) may also be patterned differently. In any case, currently used techniques for forming different patterns of shapes in different regions of the same layer, respectively, can result in the patterned shapes in at least one of the different regions having profiles that are less than optimal.